| 1. |
- Wang, S., et al.
(författare)
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Lifetime adaptive ECC in NAND flash page management
- 2017
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Ingår i: Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017. - : Institute of Electrical and Electronics Engineers (IEEE). - 9783981537093 ; , s. 1253-1256
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Konferensbidrag (refereegranskat)abstract
- NAND flash memory has decreasing storage reliability, as the density or program/erase (P/E) cycle increases. To ensure data integrity, error correction codes (ECCs) are widely employed and typically stored in the out-of-band area (OOB) of flash pages. However, the worst-case oriented ECC is largely under-utilized in the early stage (small P/E cycles), and the required ECC redundancy may be too large to fit in OOB in the late stage (high P/E cycles). In this paper, we propose LAE-FTL, which employs a lifetime-adaptive ECC scheme, to improve the performance and lifetime of NAND flash memory. LAE-FTL uses weak ECCs in the early stage and strong ECCs in the late stage to guarantee the storage reliability. Since OOB is large enough to store weak ECCs in the early stage, small and size-incremental codewords are adaptively used to improve data transfer and decoding parallelism. In the late stage, strong ECCs have to be employed and the ECC redundancies become too large to be stored in OOB. Thus, LAE-FTL stores the exceeding ECC redundancies in the data space of flash pages and stores user data in a cross-page fashion. Finally, our trace-driven simulation results show that LAE-FTL improves the read performance by up to 63.42%, compared to the worst-case oriented ECC scheme in the early stage, and significantly improve the storage reliability at low cost in the late stage.
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| 2. |
- Xiong, Q., et al.
(författare)
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Characterizing 3D floating gate NAND flash
- 2017
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Ingår i: SIGMETRICS 2017 Abstracts - Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems. - New York, NY, USA : Association for Computing Machinery (ACM). - 9781450350327 ; , s. 31-32
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Konferensbidrag (refereegranskat)abstract
- In this paper, we characterize a state-of-The-Art 3D oating gate NAND ash memory through comprehensive experiments on an FPGA platform. Then, we present distinct observations on performance and reliability, such as operation latencies and various error patterns. We believe that through our work, novel 3D NAND ash-oriented designs can be developed to achieve better performance and reliability.
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| 3. |
- Xiong, Q., et al.
(författare)
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Extending Real-Time Analysis for Wormhole NoCs
- 2017
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Ingår i: IEEE Transactions on Computers. - : IEEE Computer Society. - 0018-9340 .- 1557-9956. ; 66:9, s. 1532-1546
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Tidskriftsartikel (refereegranskat)abstract
- The delay upper-bound analysis problem is of fundamental importance to real-Time applications in Network-on-Chips (NoCs). In the paper, we revisit two state-of-The-Art analysis models for real-Time communication in wormhole NoCs with priority-based preemptive arbitration and show that the models only support specific router architectures with large buffer sizes. We then propose an extended analysis model to estimate delay upper-bounds for all router architectures and buffer sizes by identifying and analyzing the differences between upstream and downstream indirect interferences according to the relative positions of traffic flows and taking the buffer influence into consideration. Simulated evaluations show that our model supports one more router architecture and applies to small buffer sizes compared to the previous models.
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| 4. |
- Xiong, Q., et al.
(författare)
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Real-time analysis for wormhole NoC : Revisited and revised
- 2016
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Ingår i: Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. - New York, NY, USA : Association for Computing Machinery (ACM). - 9781450342742 ; , s. 75-80
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Konferensbidrag (refereegranskat)abstract
- The network delay upper-bound analysis problem is of fundamental importance to real-time applications in Network-on-Chip (NoC). In the paper, we revisit a state-of-the-art analysis model for real-time communication in wormhole NoC with priority-based preemptive arbitration and show that the model may provide pessimistic or even incorrect network delay upper-bound. We then propose a revised analysis model to correct the flaws in the previous model by further classifying indirect interference as upstream and downstream indirect interferences according to the relative positions of traffic flows and taking buffer influence into consideration. Simulated evaluations show that our model provides tighter and correct network delay upper-bound compared with the state-of-the-art model.
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| 5. |
- Zhu, Y., et al.
(författare)
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ALARM : A Location-Aware Redistribution Method to Improve 3D FG NAND Flash Reliability
- 2017
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Ingår i: 2017 IEEE International Conference on Networking, Architecture, and Storage, NAS 2017 - Proceedings. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781538634868
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Konferensbidrag (refereegranskat)abstract
- 3D NAND flash memory is enjoying an increasing popularity as it dramatically increases the bit density, presenting a grand opportunity to satisfy the growing demand on the storage capacity. However, this vertically stacked structure also introduces more serious read disturb problems compared with planar flash devices. Characterization results show that the read disturb errors on 3D floating gate (FG) MLC NAND flash chips exhibit a large discrepancy on the locations and types of pages, implying that pages should not be treated equally when designing migration schemes. This paper makes a thorough observation on read access characteristics by analyzing contemporary workloads collected from a wide range of applications with various read ratios. Based on the characterization results, we build a read disturb error model and propose a location-aware redistribution method (ALARM) that utilizes the intrinsic characteristics of the 3D floating gate NAND flash and redistributes read-hot pages to locations inducing less read disturb errors to improve its reliability. We implement the read disturb error model and our proposed design on an event-driven simulator, and the experimental results show that ALARM can reduce the maximum and average raw bit error rates (RBERs) by up to 99.49% and 91.80% with an operation overhead of 0.70%.
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